Functional decomposition using majority
暂无分享,去创建一个
[1] Elena Dubrova,et al. AIG rewriting using 5-input cuts , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).
[2] Valeria Bertacco,et al. The disjunctive decomposition of logic functions , 1997, ICCAD 1997.
[3] Robert K. Brayton,et al. DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[4] Mayler G. A. Martins,et al. Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).
[5] Giovanni De Micheli,et al. Busy man's synthesis: Combinational delay optimization with SAT , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.
[6] Snider,et al. Digital logic gate using quantum-Dot cellular automata , 1999, Science.
[7] M. Kostylev,et al. Realization of spin-wave logic gates , 2007, 0711.4720.
[8] A. Kitaev,et al. Universal quantum computation with ideal Clifford gates and noisy ancillas (14 pages) , 2004, quant-ph/0403025.
[9] Giovanni De Micheli,et al. BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[10] Giovanni De Micheli,et al. Optimizing Majority-Inverter Graphs with functional hashing , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[11] Giovanni De Micheli,et al. Design automation and design space exploration for quantum computers , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.
[12] Giovanni De Micheli,et al. LUT Mapping and Optimization for Majority-Inverter Graphs , 2016 .
[13] Robert K. Brayton,et al. ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.
[14] Karem A. Sakallah,et al. Resynthesis of multi-level circuits under tight constraints using symbolic optimization , 2002, ICCAD 2002.
[15] Victor N. Kravets,et al. Constructive library-aware synthesis using symmetries , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).
[16] Mathias Soeken,et al. Exact Synthesis of Majority-Inverter Graphs and Its Applications , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] A. Brayton. Faster Logic Manipulation for Large Designs , 2012 .
[18] Yoshihiro Tohma,et al. Decompositions of Logical Functions Using Majority Decision Elements , 1964, IEEE Trans. Electron. Comput..
[19] Giovanni De Micheli,et al. Majority-Inverter Graph: A novel data-structure and algorithms for efficient logic optimization , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[20] Giovanni De Micheli,et al. Classifying Functions with Exact Synthesis , 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).
[21] Giovanni De Micheli,et al. A novel basis for logic rewriting , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
[22] A Imre,et al. Majority Logic Gate for Magnetic Quantum-Dot Cellular Automata , 2006, Science.
[23] Sheldon B. Akers,et al. Synthesis of combinational logic using three-input majority gates , 1962, SWCT.
[24] R. A. Smith. Minimal Three-Variable NOR and NAND Logic Circuits , 1965, IEEE Trans. Electron. Comput..
[25] Zhiru Zhang,et al. A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping , 2017, FPGA.
[26] Mathias Soeken,et al. SAT-Based Combinational and Sequential Dependency Computation , 2016, Haifa Verification Conference.