Hyper-Systolic Processing on the Quadrics: Improving Inter-Processor Communication by Simulated Annealing

Systolic processing is a technique [1] to enlarge the range of aрplications of parallel computers widely, in particular for SIMD and SISAMD (single instruction — single addressing — multiple data) architectures. Its hyper-systolic extension can enhance substantially the inter-processor communication speed. The optimization of the actual hyper-systolic communication layout is a non-trivial task if more than 64 processing nodes are involved. Using Simulated Annealing techniques we are able to improve the recently used regular hyper-systolic bases. We find that the speed of inter-processor communication can be increased by about 20 % on the 25 Gflops Quadrics QH4 (with 512 compute nodes) for n2-problems.