Clock gating based energy efficient ALU design and implementation on FPGA

In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.

[1]  Luca Benini,et al.  A scalable algorithm for RTL insertion of gated clocks based on ODCs computation , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Tae Won Cho,et al.  A design of low power 16-b ALU , 1999, Proceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030).

[3]  Bishwajeet Pandey,et al.  Clock Gating Aware Low Power ALU Design and Implementation on FPGA , 2013 .

[4]  Antonio J. Acosta,et al.  Optimization of clock-gating structures for low-leakage high-performance applications , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[5]  Cindy Eisner,et al.  Resurrecting infeasible clock-gating functions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[6]  Norhayati Soin,et al.  Regional clock gate splitting algorithm for clock tree synthesis , 2010, 2010 IEEE International Conference on Semiconductor Electronics (ICSE2010).

[7]  José C. Monteiro,et al.  Optimization of combinational and sequential logic circuits for low power using precomputation , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[8]  Juan Suardíaz Muro,et al.  Rapid prototyping of a self-timed ALU with FPGAs , 2005, 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05).

[9]  B. U. V. Prashanth,et al.  Design & implementation of floating point ALU on a FPGA processor , 2012, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET).

[10]  E. Boemo,et al.  Clock gating and clock enable for FPGA power reduction , 2012, 2012 VIII Southern Conference on Programmable Logic.

[11]  S. S. Salankar,et al.  Clock gating — A power optimizing technique for VLSI circuits , 2011, 2011 Annual IEEE India Conference.

[12]  Yu-Liang Wu,et al.  On applying erroneous clock gating conditions to further cut down power , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).