Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors
暂无分享,去创建一个
[1] Cecilia Metra,et al. Novel transient fault hardened static latch , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[2] T. Calin,et al. Upset hardened memory design for submicron CMOS technology , 1996 .
[3] L. Dominik,et al. System mitigation techniques for single event effects , 2008, 2008 IEEE/AIAA 27th Digital Avionics Systems Conference.
[4] Jr. Leonard R. Rockett. An SEU-hardened CMOS data latch design , 1988 .
[5] J. Canaris,et al. SEU hardened memory cells for a CCSDS Reed-Solomon encoder , 1991 .
[6] R. Velazco,et al. Design of SEU-hardened CMOS memory cells: the HIT cell , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).
[7] D. Rossi,et al. Latch Susceptibility to Transient Faults and New Hardening Approach , 2007, IEEE Transactions on Computers.
[8] Lorena Anghel,et al. Simulation and mitigation of single event effects , 2005, 11th IEEE International On-Line Testing Symposium.