The Si–SiO2 interface: Correlation of atomic structure and electrical properties

The roughness at the Si–SiO2 interface has been determined quantitatively on an atomic scale by SPA‐LEED (spot profile analysis of low energy electron diffraction) in ultrahigh vacuum after removal of the oxide. At the Si–SiO2 interface the steps are randomly distributed. With the help of model calculations the measured spot broadening provides the step atom density and therefore the roughness on an atomic scale. The roughness will be decreased by low oxidation rates (thick oxides, dry atmosphere) and appropriate annealing in N2 and will be increased by high oxidation rates (thin oxides and wet atmosphere). Furthermore metal oxide semiconductor (MOS) structures were built on chips which were also suited for LEED measurements. Hall mobilities for Si(111) p‐channel inversion layers MOS‐FETs with varying roughness at the Si–SiO2 interface have been measured at temperatures between 4.2 K and room temperature. It was found that there exists a strong correlation between Hall mobility and atomic roughness at hig...