STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing

Abstract Spin-transfer torque magnetic tunnel junction (STT-MTJ) technology is an attractive solution for designing non-volatile Logic-in-Memory (LIM) architectures. This work explores a smart material implication (SIMPLY) LIM scheme based on nanoscale STT-MTJs. The SIMPLY architecture is benchmarked against the conventional material implication (IMPLY) logic. Obtained results prove that for similar performance the STT-MTJ based SIMPLY scheme ensures more reliable operation (i.e., lower error rate by more than three orders of magnitude) and an energy saving of −70% than its IMPLY counterpart, at the only cost of minimal area overhead.

[1]  Marco Lanuzza,et al.  A Compact Model with Spin-Polarization Asymmetry for Nanoscaled Perpendicular MTJs , 2017, IEEE Transactions on Electron Devices.

[2]  Jeong-Heon Park,et al.  Dependence of Voltage and Size on Write Error Rates in Spin-Transfer Torque Magnetic Random-Access Memory , 2016, IEEE Magnetics Letters.

[3]  Siegfried Selberherr,et al.  Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory , 2013 .

[4]  Paolo Pavan,et al.  Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices , 2020, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[5]  Massimo Alioto,et al.  A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  H. Ohno,et al.  A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction. , 2010, Nature materials.

[7]  Gregory S. Snider,et al.  ‘Memristive’ switches enable ‘stateful’ logic operations via material implication , 2010, Nature.

[8]  Marco Lanuzza,et al.  Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework , 2017, IEEE Transactions on Nanotechnology.

[9]  Youguang Zhang,et al.  A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network , 2018, IEEE Transactions on Magnetics.

[10]  Anand Raghunathan,et al.  Computing in Memory With Spin-Transfer Torque Magnetic RAM , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Marco Lanuzza,et al.  Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework , 2019 .

[12]  Mircea R. Stan,et al.  The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory , 2010, Proceedings of the IEEE.

[13]  D. Ralph,et al.  Measurement of the spin-transfer-torque vector in magnetic tunnel junctions , 2007, 0705.4207.

[14]  Martin Margala,et al.  Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[15]  Junjie Li,et al.  In-memory direct processing based on nanoscale perpendicular magnetic tunnel junctions. , 2018, Nanoscale.

[16]  Marco Lanuzza,et al.  Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework , 2020, Integr..

[17]  F. Puglisi,et al.  Smart Logic-in-Memory Architecture for Low-Power Non-Von Neumann Computing , 2020, IEEE Journal of the Electron Devices Society.

[18]  Paolo Pavan,et al.  SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model , 2019, ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC).

[19]  Lirida A. B. Naviner,et al.  Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Yiran Chen,et al.  Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes , 2015, IEEE Transactions on Electron Devices.

[21]  Siegfried Selberherr,et al.  Reliability Analysis and Comparison of Implication and Reprogrammable Logic Gates in Magnetic Tunnel Junction Logic Circuits , 2013, IEEE Transactions on Magnetics.