A RECONFIGURABLE W.S.I. NEURAL NETWORK
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This paper presents a WSI neural network. The solution we present consists of implementing the N neuron Hopfield network as a systolic square array made up of N* cells. Systolic arrays are well-suited to WSI. Furthermore, inherent error tolerance of neural networks makes easier the wafer design. However a wafer level reconfiguration is required to bypass faulty chips. We describe the principle and the architecture of a switching element which provides a flexible wafer level reconfiguration.
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