TMR voting in the presence of crosstalk faults at the voter inputs

In high reliability systems, the effectiveness of fault tolerant techniques, such as Triple-Modular-Redundancy (TMR), must be validated with respect to the faults that are likely in the current technology. In todays' Integrated Circuits (IC), this is the case of crosstalks, whose importance is growing because of device & interconnect scaling. This paper analyzes the problem of crosstalk faults at the inputs of voters in TMR systems. In particular, possible problems are illustrated, and it is shown that such crosstalk may invalidate the reliability of both voting, and diagnosing operations. The problem is analyzed from a probabilistic point of view. Its occurrence is estimated by using a set of TMR systems obtained with combinational benchmarks as functional modules. The possible problems of such operations are discussed in the presence of crosstalk faults. It is shown that crosstalk may invalidate the reliability of both voting, and diagnosis operations. A probabilistic model of the voting & diagnosis operations in the presence of crosstalk has been developed. Finally, such a model has been used to estimate the probability of voting & diagnosis failures in a set of TMR systems obtained by using combinational benchmarks as functional modules. We have shown that the presence of crosstalk faults at voter inputs may impair both the voting, and the diagnosis mechanisms. This problem has been quantified by applying a probabilistic model of crosstalk fault effects on voting and diagnosis to a set of benchmark circuits. Results show that crosstalk may create a reliability problem for TMR systems. Such a problem can be solved by using on-line testing or design for testability providing additional controllability & observability to the replicated functional units.

[1]  Charles E. Stroud,et al.  Testability and test generation for majority voting fault-tolerant circuits , 1993, J. Electron. Test..

[2]  Nikolaos Gaitanis The Design of Totally Self-Checking TMR Fault-Tolerant Systems , 1988, IEEE Trans. Computers.

[3]  Yvon Savaria,et al.  Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays , 1996 .

[4]  M. Soma,et al.  Crosstalk and transient analyses of high-speed interconnects and packages , 1991 .

[5]  Charles E. Stroud,et al.  Applying built-in self-test to majority voting fault tolerant circuits , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[6]  Melvin A. Breuer,et al.  Analytic models for crosstalk delay and pulse analysis under non-ideal inputs , 1997, Proceedings International Test Conference 1997.

[7]  Cecilia Metra,et al.  Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Cecilia Metra,et al.  On-line detection of logic errors due to crosstalk, delay, and transient faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Hagbae Kim,et al.  A Time Redundancy Approach to TMR Failures Using Fault-State Likelihoods , 1994, IEEE Trans. Computers.

[10]  Melvin A. Breuer,et al.  Process variations and their impact on circuit operation , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[11]  Tassos Markas,et al.  Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Charles E. Stroud,et al.  Design for testability and test generation for static redundancy system level fault-tolerant circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[13]  Irith Pomeranz,et al.  Testing of Fault-Tolerant Hardware Through Partial Control of Inputs , 1993, IEEE Trans. Computers.

[14]  Xiaole Xu,et al.  An approach to the analysis and detection of crosstalk faults in digital VLSI circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[16]  Kyung Tek Lee,et al.  Test generation for crosstalk effects in VLSI circuits , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[17]  Wojciech Maly,et al.  Future of testing: Reintegration of design, testing and manufacturing , 1996, Proceedings ED&TC European Design and Test Conference.

[18]  Antonio Rubio,et al.  Spurious signals in digital CMOS VLSI circuits: a propagation analysis , 1992 .

[19]  Melvin A. Breuer,et al.  Test generation in VLSI circuits for crosstalk noise , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[20]  Sujit Dey,et al.  Analysis of interconnect crosstalk defect coverage of test sets , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[21]  Cecilia Metra,et al.  Compact and low power on-line self-testing voting scheme , 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[22]  Sung-Mo Kang,et al.  Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits , 1990 .

[23]  Cecilia Metra,et al.  Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines , 2000, IEEE Trans. Computers.

[24]  Israel Koren,et al.  The effect of spot defects on the parametric yield of long interconnection lines , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

[25]  Dhiraj K. Pradhan,et al.  Fault-tolerant computing : theory and techniques , 1986 .

[26]  Kurt Keutzer,et al.  Getting to the bottom of deep submicron , 1998, ICCAD '98.

[27]  Salim Chowdhury,et al.  An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines , 1992, ICCAD.