A mm-Wave Switched-Capacitor RFDAC
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[1] Jinho Ko,et al. A Single-Supply Single-Core Inverse Class-D Digital Power Amplifier with Enhanced Power Back-Off Efficiency Adopting Output Power Scaling Technique , 2021, 2021 Symposium on VLSI Circuits.
[2] Jeffrey S. Walling,et al. An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS , 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Hongtao Xu,et al. A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement , 2021, IEEE Journal of Solid-State Circuits.
[4] Aoyang Zhang,et al. 26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency , 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).
[5] Hao Min,et al. A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement , 2020, IEEE Journal of Solid-State Circuits.
[6] J. Walling,et al. Leveraging Programmable Capacitor Arrays for Frequency-Tunable Digital Power Amplifiers , 2020, IEEE Transactions on Microwave Theory and Techniques.
[7] James F. Buckwalter,et al. A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation , 2020, IEEE Journal of Solid-State Circuits.
[8] Fei Wang,et al. 24.1 A 24-to-30GHz Watt-Level Broadband Linear Doherty Power Amplifier with Multi-Primary Distributed-Active-Transformer Power-Combining Supporting 5G NR FR2 64-QAM with >19dBm Average Pout and >19% Average PAE , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).
[9] Sensen Li,et al. 24.3 A 28GHz Current-Mode Inverse-Outphasing Transmitter Achieving 40%/31% PA Efficiency at Psat/6dB PBO and Supporting 15Gbit/s 64-QAM for 5G Communication , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).
[10] Mike Shuo-Wei Chen,et al. A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier , 2019, IEEE Journal of Solid-State Circuits.
[11] Y. Palaskas,et al. A Cellular Multiband DTC-Based Digital Polar Transmitter With −153 dBc/Hz Noise in 14-nm FinFET , 2019, IEEE Solid-State Circuits Letters.
[12] Hua Wang,et al. A 28-GHz Flip-Chip Packaged Chireix Transmitter With On-Antenna Outphasing Active Load Modulation , 2019, IEEE Journal of Solid-State Circuits.
[13] Fei Wang,et al. 4.8 A Highly Linear Super-Resolution Mixed-Signal Doherty Power Amplifier for High-Efficiency mm-Wave 5G Multi-Gb/s Communications , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).
[14] Wen Yuan,et al. 4.3 A Multiphase Interpolating Digital Power Amplifier for TX Beamforming in 65nm CMOS , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).
[15] Jeffrey S. Walling,et al. Corrections to “Split-Array, C-2C Switched-Capacitor Power Amplifiers” , 2018, IEEE Journal of Solid-State Circuits.
[16] Hua Wang,et al. A continuous-mode harmonically tuned 19-to-29.5GHz ultra-linear PA supporting 18Gb/s at 18.4% modulation PAE and 43.5% peak PAE , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).
[17] Sorin P. Voinigescu,et al. Ultra-Broadband I/Q RF-DAC Transmitters , 2017, IEEE Transactions on Microwave Theory and Techniques.
[18] Voravit Vorapipat,et al. A Class-G Voltage-Mode Doherty Power Amplifier , 2017, IEEE Journal of Solid-State Circuits.
[19] Kaushik Dasgupta,et al. A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS , 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.
[20] Elad Alon,et al. A 65nm CMOS I/Q RF power DAC with 24–42dB 3rd harmonic cancellation and up to 18dB mixed-signal filtering , 2017, 2017 Symposium on VLSI Circuits.
[21] Jeffrey S. Walling,et al. A Multiphase Switched Capacitor Power Amplifier , 2017, IEEE Journal of Solid-State Circuits.
[22] Hyung Seok Kim,et al. 13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[23] Fei Wang,et al. 2.1 A 28GHz/37GHz/39GHz multiband linear Doherty power amplifier for 5G massive MIMO applications , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[24] Sherif Shakib,et al. 2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[25] Harald Pretl,et al. 13.2 A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 28nm CMOS , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[26] Chunshu Li,et al. Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication , 2016, IEEE Journal of Solid-State Circuits.
[27] Jeffrey S. Walling,et al. A Quadrature Switched Capacitor Power Amplifier , 2016, IEEE Journal of Solid-State Circuits.
[28] Robert Bogdan Staszewski,et al. A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS , 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
[29] S. M. Alavi,et al. All-Digital I/Q RF-DAC , 2014 .
[30] Sorin P. Voinigescu,et al. A 19 dBm, 15 Gbaud, 9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters , 2014, IEEE Journal of Solid-State Circuits.
[31] Robert Bogdan Staszewski,et al. All-Digital RF $I/Q$ Modulator , 2012 .
[32] Marian Verhelst,et al. A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.
[33] Q. J. Gu,et al. Two-Way Current-Combining $W$-Band Power Amplifier in 65-nm CMOS , 2012, IEEE Transactions on Microwave Theory and Techniques.
[34] Jeffrey S. Walling,et al. A Switched-Capacitor RF Power Amplifier , 2011, IEEE Journal of Solid-State Circuits.
[35] O. Degani,et al. A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.
[36] S.L.J. Gierkink,et al. Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump , 2008, IEEE Journal of Solid-State Circuits.
[37] M. Spong,et al. On Synchronization of Kuramoto Oscillators , 2005, Proceedings of the 44th IEEE Conference on Decision and Control.
[38] R.B. Staszewski,et al. A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS , 2005, 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers.
[39] O. Lee,et al. A Highly Efficient and Linear mm-Wave CMOS Power Amplifier Using a Compact Symmetrical Parallel–Parallel Power Combiner With IMD3 Cancellation for 5G Applications , 2021, IEEE Access.