Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning

A new technique for spatial and temporal partitioning of a logic circuit simulation, based on the nodes activity computed at an higher level of abstraction is presented in this paper. Only those components who are sensitized by a given input vector are added to the detailed netlist for electric simulation. The methodology is suitable for parallel implementation on a multi-processor environment and allows one to arbitrarily switch between fast and detailed level of abstraction during the simulation run. This technique has been successfully applied, among the others, to the verification of a fully synthesizable IP designed to achieve the optimal implementation of a Viterbi decoder over a wide range of parametric circuit configurations. The experimental results obtained on a further significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory allocation and yet keeping the high accuracy which is peculiar of the electric simulation. In addition, the proposed technique easily fits in the existing industrial verification flows.