Design of frame buffer for 1 THz energy efficient digital image processor based on HSLVDCI I/O standard in FPGA

This paper proposes design of frame buffer for a digital image processor. This design is implemented on Virtex-6 Field Programmable Gate Array (FPGA). In this work, three classes of High-Speed Low Voltage Digitally Controlled Impedance (HSLVDCI) are used to compare dynamic power requirements for the frame buffer. The experiment is performed at 1 GHz, 10 GHz, and 100 GHz and 1 THz device frequencies. The power utilization of the frame buffer is compared to find out the most energy efficient class of HSLVDCI. Dynamic power consists of clock power, logic power, signal power and I/O power. I/O power is higher than any other dynamic power, whereas logic power is the least used dynamic power. It is observed that the power requirements for clock, logic and signal are same for all the three I/O standards. There is an increase in I/O power with the increase in reference voltage of I/O standard. When frame buffer is operating at 1 GHz, the reduction in I/O power requirement of HSLVDCI_18 is 36.84% and of HSLVDCI_15 is 52.63% as compared to HSLVDCI_25. There is an improvement of 36.17% and 53.19% in I/O power when implemented with HSLVDCI_18 and HSLVDCI_15 respectively, as compared to HSLVDCI_25, at 10 GHz. When operating at 100 GHz, there is a reduction of 36.08%, 53.14% in I/O power of HSLVDCI_18 and HSLVDCI_15 respectively as compared to HSLVDCI_25. Also, the I/O power required by HSLVDCI_18 and HSLVDCI_15 is 36.09%, 53.14% lower respectively, than required in HSLVDCI_25, for the case of 1THz operating frequency.

[1]  M. Lukowiak,et al.  Methodology and optimizing of multiple frame format buffering within FPGA H.264/AVC decoder with FRExt , 2008, 2008 15th International Conference on Mixed Design of Integrated Circuits and Systems.

[2]  J. Yadav,et al.  Energy efficient design and implementation of ALU on 40nm FPGA , 2013, 2013 International Conference on Energy Efficient Technologies for Sustainability.

[3]  S. A. Milinkovic.  Software JPEG decoder for embedded systems , 2012, 2012 20th Telecommunications Forum (TELFOR).

[4]  Walter Stechele,et al.  Partitioning and context switching for a reconfigurable FPGA-based DAB receiver , 2012, Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing.

[5]  P. Kannan.  Fundamental blocks of single ended LVCMOS output buffer- a circuit level design guideline , 2007, 2007 18th European Conference on Circuit Theory and Design.

[6]  Yun Pan,et al.  Adaptive memory architecture for real-time image warping , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[7]  Bishwajeet Pandey,et al.  Low voltage DCI based low power VLSI circuit implementation on FPGA , 2013, 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES.

[8]  Barmak Honarvar,et al.  Efficient Hardware Accelerators for the Computation of Tchebichef Moments , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[9]  Naehyuck Chang,et al.  A compressed frame buffer to reduce display power consumption in mobile systems , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[10]  Ángel Rodríguez-Vázquez,et al.  A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors , 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

[11]  Bishwajeet Pandey,et al.  Clock gated low power sequential circuit design , 2013, 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES.

[12]  P. Kannan,et al.  Aspects and solutions to designing standard LVCMOS I/O buffers in 90nm process , 2007, AFRICON 2007.