High-level synthesis assisted rapid prototyping for digital signal processing

The increasing needs of higher data rates associated with mobility constraints motivate the development of digital satellite news gathering (DSNG) and digital video broadcasting applications by satellite (DVB/spl I.bar/S). Error control codes like Reed-Solomon and Viterbi codes are widely used in these communication systems against channel noise. Traditional methods for rapid prototyping of hardware cores for this kind of applications are based on RTL specifications. However, they suffer from heavy limitations that prevent them from efficiently addressing both the algorithmic complexity and the high flexibility required by the various application profiles in fast implementation and prototyping issues. For this reasons, we propose to reduce hardware IP core development time by benefiting from the emerging high-level synthesis (HLS) tools in a platform-based approach dedicated to rapid prototyping. This technique has been successfully applied to the design of Reed-Solomon (RS) and Viterbi decoder IP cores for the DVB-DSNG standard and can be easily extended to many DSP dataflow applications.