Pipelined belief propagation polar decoders

Due to its inherent higher parallelism over successive cancellation (SC) polar decoder, belief propagation (BP) polar decoder becomes more favorable for high throughput applications. However, most existing BP decoders suffer from low utilization. In this paper, a new updating scheme, in which both left-to-right and right-to-left messages are considered identical, is first proposed for memory reduction. By revealing the similarity between BP polar decoder and fast Fourier transform (FFT) processor, both feed-forward and feed-back pipelined BP polar decoders are proposed along with detailed processing schedules. Implementation results have shown that both proposed pipelined BP decoders achieve more than 99.8% arithmetic logical units (ALUTs) reduction and 3.40% registers & block memory reduction, together with more than 7.45% speed-up, compared to the conventional fully parallel one. The proposed design approaches can be generalized with folding technique to achieve the required balance between area and speed flexibly.