Design of 16-Bit Low Power Carry Select Adder using D-Flip Flop

Adder circuits are the basic component for any of the processors like digital signal processors. An area and lower consumption efficient adder design are necessary for the high speed applications. In the data path operation, propagation of the carry through the adder is a critical section. Carry select adder (CSA) is efficient for the low power applications, produces the partial sum and carry by independently generating multiple carries. Hence, there is a chance in the CSA to reducing the area and power consumption. Conventional CSA uses the two pair of ripple carry adder (RCA) with cin = 0 and cin = 1 hence consumes more power. Complimentary pass transistor based CSA designed using inverter at the input side to drive the gate of MOS transistors and the output side to strengthen the signal therefore it’s not an area efficient. The proposed carry select adder uses the true single phase clock (TSPC) D-Flip flop instead of using RCA and BEC in the conventional method. This saves a significant area and power with reduced number of transistors. The proposed 16-bit adder design is implemented in semi custom 180-nm technologies which save 75% and 25% of the power over the conventional adder and normal TSPC based adder respectively. The proposed adder is good candidate for the power delay product which reduced to 75% and 50% over the conventional based RCA and normal TSPC adder respectively. stify;text-justify:inter-ideograph; line-height:normal'> It is purely based on the secondary data and tries to highlight the issues and challenges faced by Indian companies in implementation of CSR as a tool in the economic development. l areas. The model showed that inter alia an extension centre and a mission-oriented programme would be required to develop technologies to address the normally ignored felt needs of the rural population. While many crucial features of this initial ASTRA model have been validated, it also had several shortcomings that are described. An attempt has been made in this paper to indicate some directions along which the model should be updated taking into account the emphasis today on sustainable development. Special attention has been devoted to the failure modes in the generation, commercialisation and dissemination of rural technologies. Finally, the barriers to the commercialisation and dissemination of rural technologies are discussed.