LDBR: Low-deflection bufferless router for cost-sensitive network-on-chip design

Abstract In network-on-chip (NoC) designs, the bufferless router is more energy-efficient than the conventional router with buffers. However, in the bufferless network, deflections cause great performance loss. In this paper, three deflection models are firstly constructed for analyzing the causes of deflections. Then, we propose a low-deflection bufferless router (LDBR), in which a multi-channel network interface and a novel deflection routing based on turn model are designed for reducing the deflections during packet transmissions. Finally, LDBR is evaluated against the latest bufferless routers using synthetic and real-world traffic patterns. The experimental results exhibit that the deflection rate of LDBR network is reduced by 41% compared to other bufferless networks, and LDBR also shows superiority in cost and power consumption across all workloads.

[1]  Andreas Herkersdorf,et al.  Benefits of selective packet discard in networks-on-chip , 2012, TACO.

[2]  Loren Schwiebert,et al.  A Necessary and Sufficient Condition for Deadlock-Free Wormhole Routing , 1996, J. Parallel Distributed Comput..

[3]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1992, ISCA '92.

[4]  Sriram R. Vangal,et al.  A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.

[5]  Pedro López,et al.  Reducing Packet Dropping in a Bufferless NoC , 2008, Euro-Par.

[6]  Kevin Kai-Wei Chang,et al.  HAT: Heterogeneous Adaptive Throttling for On-Chip Networks , 2012, 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing.

[7]  P. Baran,et al.  On Distributed Communications Networks , 1964 .

[8]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[9]  Doug Burger,et al.  Implementation and Evaluation of On-Chip Network Architectures , 2006, 2006 International Conference on Computer Design.

[10]  Seung Eun Lee,et al.  A variable frequency link for a power-aware network-on-chip (NoC) , 2009, Integr..

[11]  John L. Henning.  SPEC CPU2000: Measuring CPU Performance in the New Millennium , 2000, Computer.

[12]  John Jose,et al.  DeBAR: Deflection based adaptive router with minimal buffering , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[14]  Henry Hoffmann,et al.  Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[15]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[16]  John Kim,et al.  Low-cost router microarchitecture for on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[17]  George Michelogiannakis,et al.  Evaluating Bufferless Flow Control for On-chip Networks , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

[18]  Chris Fallin,et al.  CHIPPER: A low-complexity bufferless deflection router , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[19]  Jun Yang,et al.  Simple virtual channel allocation for high throughput and high frequency on-chip routers , 2010, HPCA.

[20]  Gul N. Khan,et al.  Designing power and performance optimal application-specific Network-on-Chip architectures , 2011, Microprocess. Microsystems.

[21]  Onur Mutlu,et al.  A case for bufferless routing in on-chip networks , 2009, ISCA '09.

[22]  George Michelogiannakis,et al.  Elastic-buffer flow control for on-chip networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[23]  Kevin Kai-Wei Chang,et al.  MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[24]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[25]  Natalie D. Enright Jerger,et al.  SCARAB: A single cycle adaptive routing and bufferless network , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[26]  Sharad Malik,et al.  Power-driven design of router microarchitectures in on-chip networks , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[27]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[28]  Luca Benini,et al.  Powering networks on chips , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[29]  T. N. Vijaykumar,et al.  Adaptive Flow Control for Robust Performance and Energy , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[30]  George Michelogiannakis,et al.  Elastic Buffer Flow Control for On-Chip Networks , 2013, IEEE Transactions on Computers.

[31]  Natalie D. Enright Jerger,et al.  Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support , 2008, 2008 International Symposium on Computer Architecture.

[32]  Chris Fallin,et al.  Next generation on-chip networks: what kind of congestion control do we need? , 2010, Hotnets-IX.