Test sequences to achieve high defect coverage for synchronous sequential circuits

Test sets that detect each stuck-at fault n>1 times (called n-detection stuck-at test sets) were shown to be effective in achieving high defect coverages. In addition, a pseudofunctional fault model defined before was shown to result in test sets having similar defect coverages. Previous studies of n-detection stuck-at test sets and pseudofunctional test sets were for combinational circuits, In this paper, we study detection stuck-at test sequences and pseudofunctional test sequences for synchronous sequential circuits. Considering stuck-at faults, we propose five definitions of the number of detections achieved by a test sequence. These definitions lead to five different definitions of n-detection stuck at test sequences. We discuss the effects of these definitions on fault-simulation and test-generation procedures and present experimental results for benchmark circuits to evaluate their relative effectiveness. The experimental results indicate the usefulness of the simplest definition in generating test sequences that achieve improved defect coverages. We also describe a pseudofunctional fault model that extends previous definitions. We describe fault-simulation and test-generation methods for this model and give experimental data to evaluate its effectiveness. The results indicate that this model too can be used to generate test sequences with improved defect coverage. Its advantages and disadvantages compared to the n-detection stuck-at model are also considered.

[1]  Irith Pomeranz,et al.  On the effects of test compaction on defect coverage , 1996, Proceedings of 14th VLSI Test Symposium.

[2]  Mark W. Levi,et al.  CMOS Is Most Testable , 1981, International Test Conference.

[3]  Irith Pomeranz,et al.  Vector restoration based static compaction of test sequences for synchronous sequential circuits , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[4]  Irith Pomeranz,et al.  COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[5]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[6]  M. Ray Mercer,et al.  On the decline of testing efficiency as fault coverage approaches 100% , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[7]  Kewal K. Saluja,et al.  Fast test generation for sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[9]  Irith Pomeranz,et al.  On static compaction of test sequences for synchronous sequential circuits , 1996, DAC '96.

[10]  Tracy Larrabee,et al.  Test Pattern Generation for Realistic Bridge Faults in CMOS ICs , 1991, 1991, Proceedings. International Test Conference.

[11]  Irith Pomeranz,et al.  On generating compact test sequences for synchronous sequential circuits , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[12]  Janak H. Patel,et al.  Compaction of ATPG-generated test sequences for sequential circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[13]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[14]  Edward J. McCluskey,et al.  Design for Autonomous Test , 1981, IEEE Transactions on Computers.