Address Sequences Generation for Multiple Run Memory Testing

This paper deals with address generation for multiple run memory tests. It presents the algorithms for address sequences generation and proposes the new method for address sequences generation. The experimental results with the proposed address sequence are also shown.

[1]  de Ng Dick Bruijn.  A combinatorial problem , 1946 .

[2]  Carla Savage,et al.  A Survey of Combinatorial Gray Codes , 1997, SIAM Rev..

[3]  Svetlana V. Yarmolik,et al.  Address sequences for march tests to detect pattern sensitive faults , 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).

[4]  S.V. Yarmolik,et al.  Modified Gray And Counter Sequences For Memory Test Address Generation , 2006, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006..

[5]  Svetlana V. Yarmolik,et al.  Optimal Memory Address Seeds for Pattern Sensitive Faults Detection , 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

[6]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .