On Reachable State Space Reduction for Formal Validation of Scan-based Systems

In search for optimal validation techniques, researchers try to simplify the modeling and analysis processes. Generally, the simplification is based on compact and focused problem representation, where the information may be abstracted according to the set of predefined constrains. This paper discusses the application of state space reduction to formal models of a scan-based system and in particular to programmable logic controller (PLC).

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