LogicBuilt-In Self-Test forCore-Based Designs onSystem-on-a-Chip

System-on-a-chip (SoC)built withembeddedIP coresoffersattractive methodology designreuse, reconfigurability, andcustomizability. Butintegration of design-for-testability (DfT)structures ofIPcoresinthese complex SoCspresents daunting challenges todesigners and ultimately affects thetime-to-market goals. Inthis paper, we introduce adesign methodology toreduce thetime-to-market bytaking coretestdatafromthedesign environment and automatically generating DfTstructures thatcanbeeasily integrated intoSoC. A novelautomatedsynthesis methodology togenerate SoCbuilt-in self-test (BIST)in ordertotestIPandcustomlogic coreswithhighfault coverage isproposed. Theproposed technique, modified configurable 2-DLFSR,ismodeledafter theprinciple of configurable 2-D LFSR design, whichgenerates a deterministic sequence oftestvectors forrandom-vector- resistant faults, andthenrandomtest vectors forrandom- vector-detectable faults. Thebasis ofthis methodistoexplore thedesign solution spaceforoptimal 2-DLFSRdesign by replacing theXOR gatesusedintheconventional LFSRs withsimple logic gates like NOR andNAND.Moreover, the proposed approach iscapable ofoptimizing 2-DLFSRswith consideration ofdon't-care bits inincompletely specified test patterns.