A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Modulator

A time-to-digital converter (TDC) is proposed to re- place the multi-bit quantizer and the multi-bit feedback DAC of traditionalvoltage-mode modulator.Sincetime-modesystems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ADC digital friendly and more suitable for nano- metrictechnologies.Apulse-width-modulator(PWM)convertsthe sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC gen- erates a digital code that corresponds to the pulse width. Simulta- neously, the TDC provides a time-quantized feedback pulse for the modulator, emulating the voltage-DAC in a conventional ADC.Linearity,jitteranddata-dependent-delayeffectsontheper- formance of the proposed architecture are analyzed. A chip proto- typeis fabricated in TI 65 nmdigitalCMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the -modulator achievesadynamicrangeof68dBandtheTDCconsumes5.66mW at 250 MHz event rate while occupying 0.006 mm .

[1]  Timo Rahkonen,et al.  A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method , 2009, IEEE Journal of Solid-State Circuits.

[2]  Stephan Henzler,et al.  A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion , 2008, IEEE Journal of Solid-State Circuits.

[3]  Stephan Henzler,et al.  Time-to-Digital Converters , 2010 .

[4]  Rong Zhou,et al.  A simple smart time-to-digital convertor based on vernier method for a high resolution LYSO MicroPET , 2007, 2007 IEEE Nuclear Science Symposium Conference Record.

[5]  K. Karadamoglou,et al.  An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments , 2004, IEEE Journal of Solid-State Circuits.

[6]  Maarten Vertregt,et al.  Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures , 2001 .

[7]  J. Yugami,et al.  Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[8]  Edgar Sánchez-Sinencio,et al.  A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  F. Dell'ova,et al.  Analog phase measuring circuit for digital CMOS ICs , 1993 .

[10]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[11]  Edgar Sánchez-Sinencio,et al.  A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element , 2011, IEEE Journal of Solid-State Circuits.

[12]  P. Madhani,et al.  Impact of Sinter Process and Metal Coverage on Transistor Mismatching and Parameter Variations in Analog CMOS Technology , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

[13]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines for the digitization of short time intervals , 1993 .

[14]  Yannis Tsividis,et al.  Continuous-time digital signal processing , 2003 .

[15]  Stephan Henzler,et al.  90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[16]  Y. Arai,et al.  Development of a CMOS time memory cell VLSI and a CAMAC module with 0.5 ns resolution , 1991, Conference Record of the 1991 IEEE Nuclear Science Symposium and Medical Imaging Conference.

[17]  S. F. Dow,et al.  A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip , 1995 .

[18]  Edgar Sánchez-Sinencio,et al.  A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique , 2010, IEEE Journal of Solid-State Circuits.