Design of Architecture for Sampling Rate Converter of Demodulator

This paper proposes a novel architecture for sampling rate converter of the demodulator for processing satellite data communication. The overall receiver algorithm is divided into two parts: one to be implemented on an FPGA and the other on a DSP processor. A new distributed arithmetic based architecture for implementing a Sampling Rate Converter is also proposed. The main advantage of this architecture is that it does not employ any MAC unit, whose operational speed is, generally, a bottleneck for high filter throughput. Instead, it makes extensive use of LUTs and hence is ideally suited for FPGA implementation. The main design goals in this work were to maintain low system complexity and reduce power consumption and chip area requirements.

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