SS-SERA: An improved framework for architectural level soft error reliability analysis

Integrated with an improved architectural vulnerability factor (AVF) computing model, a new architectural level soft error reliability analysis framework, SS-SERA (soft error reliability analysis based on SimpleScalar), was developed. SS-SERA was used to estimate the AVFs for various on-chip structures accurately. Experimental results show that the AVFs of issue queue (IQ), register update units (RUU), load store queue (LSQ) and functional unit (FU) are 38.11%, 22.17%, 23.05% and 24.43%, respectively. For address-based structures, i.e., level1 data cache (L1D), DTLB, level2 unified cache (L2U), level1 instruction cache (L1I) and ITLB, AVFs of their data arrays are 22.86%, 27.57%, 14.80%, 8.25% and 12.58%, lower than their tag arrays’ AVFs which are 30.01%, 28.89%, 17.69%, 10.26% and 13.84%, respectively. Furthermore, using the AVF values obtained with SS-SERA, a qualitative and quantitative analysis of the AVF variation and predictability was performed for the structures studied. Experimental results show that the AVF exhibits significant variations across different structures and workloads, and is influenced by multiple microarchitectural metrics and their interactions. Besides, AVFs of SPEC2K floating point programs exhibit better predictability than SPEC2K integer programs.

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