Fault Tolerance in BiNoC

For fault-tolerant data-link connections, a novel Bi-directional Fault-Tolerant NoC (BFT-NoC) scheme that supports both static and dynamic channel failures is proposed in this chapter. Except for a little performance loss, BFT-NoC can keep the system in normal operation when multiple communication channels are either permanently broken or temporarily failed in an on-chip network. In contrast to the conventional fault-tolerant schemes based on detouring packets, the operation of BFT-NoC is transparent to the adopted routing algorithm. That is, BFT-NoC can be more seamless and efficient since changing routing rules between normal and fault-tolerant operation modes is needless. Accordingly, it is possible for BFT-NoC to perform better in both resource utilization and application feasibility compared with other detour-based schemes.

[1]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[2]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[3]  Siamak Mohammadi,et al.  A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[4]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[5]  Martin Radetzki,et al.  Fault Tolerant Network on Chip Switching With Graceful Performance Degradation , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  David Blaauw,et al.  A highly resilient routing algorithm for fault-tolerant NoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[7]  Yu Hen Hu,et al.  BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[8]  Srinivas Devadas,et al.  Oblivious Routing in On-Chip Bandwidth-Adaptive Networks , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.

[9]  Alain Greiner,et al.  A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[10]  George Michelogiannakis,et al.  Evaluating Bufferless Flow Control for On-chip Networks , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

[11]  Wolfgang Rosenstiel,et al.  Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures , 2007 .