A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm/spl times/6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-/spl mu/m 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network.

[1]  George Varghese,et al.  The design of a low energy FPGA , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[2]  H. Takahashi,et al.  A 1 V DSP for wireless communications , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[3]  Jan M. Rabaey,et al.  Ultra-low-power domain-specific multimedia processors , 1996, VLSI Signal Processing, IX.

[4]  Hui Zhang,et al.  Low-swing interconnect interface circuits , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[5]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[6]  Jan M. Rabaey,et al.  Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs , 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

[7]  H. Zhang,et al.  A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[8]  Naresh R. Shanbhag,et al.  Low-power equalizers for 51.84 Mb/s very-high-speed digital subscriber loop (VDSL) modems , 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

[9]  Jan M. Rabaey,et al.  Configuration code generation and optimizations for heterogeneous reconfigurable DSPs , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[10]  George Varghese,et al.  Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System , 2001, J. VLSI Signal Process..