A high-speed low-power pipelined Viterbi Decoder: breaking the ACS-bottleneck

In this paper, a new high-speed low-power pipelined Add Select-Compare (AS-C) method and its architecture is proposed for a high throughput Viterbi Decoder (VD). The proposed pipelined AS-C unit breaks the Add-Compare-Select (ACS) recursion of the close-loop with a small area overhead, and uses the pipeline to improve the speed power of VD. After we verified the function and made the platform by FPGA, we also used UMC 0.18µm 1.8V 1P6M Standard Cell Library to implement it. With implementation by using UMC 0.18µm 1.8V Standard Cell Library, the proposed VD can improve the data rate up to 1Gbps for decoding a (3,1,2) convolutional code. To compare with the traditional VD without normalization, the proposed VD is improved by 500% in decoding speed and reduced by 60% in power consumption. Furthermore, the chip area of the new VD is reduced by 45% as compared to the traditional one. Under the 1.22V power supply and the same data rate, the proposed VD also reduces power consumption by about 54%. The operational speed of the proposed VD is up to 1GHz. Under 1GHz operation, the proposed VD consumes 15.7mW in power and the chip area utilized is about 130µm*130µm.

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