Testability of asynchronous timed control circuits with delay assumptions

This paper addresses the testability of “timed” asynchronous control circuits built of standard logic cells, in which each gate’s rise and fall time is associated with a pair of minimum and maximum values. The circuit that we analyze is assumed to be hazardfie. given that the gate delay assumptions are met in its implementation. We first give sufficient and necessary conditions under which the affects of single stuck-at-faults (SAFs) can be characterized. Then we provide sufficient conditions which ensure that these faults can be detected without access to the memory elements. Finally we present an automated tool which analyzes the testability of “timed” asynchronous circuits based on the derived conditions.