A fully scaled submicrometer NMOS technology using direct-write E-beam lithography

Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET's, including a study of nonscaling effects and their impact on the device and circuit design.

[1]  R. Dennard,et al.  A Fully Scaled Half-Micrometer NMOS Technology Using Direct-Write E-Beam Lithography , 1984, 1984 Symposium on VLSI Technology. Digest of Technical Papers.

[2]  J. Lohstroh,et al.  Worst-case static noise margin criteria for logic circuits and their mathematical equivalence , 1983, IEEE Journal of Solid-State Circuits.

[3]  G. Baccarani,et al.  Transconductance degradation in thin-Oxide MOSFET's , 1983, IEEE Transactions on Electron Devices.

[4]  MOS Device and Technology Constraints in VLSI , 1982, IEEE Journal of Solid-State Circuits.

[5]  W.R. Hunter,et al.  Enhanced-performance 4K × 1 high-speed SRAM using optically defined submicrometer devices in selected circuits , 1982, IEEE Transactions on Electron Devices.

[6]  Y. El-Mansy.  MOS Device and technology constraints in VLSI , 1982, IEEE Transactions on Electron Devices.

[7]  R.H. Dennard,et al.  Alpha-Particle-Induced Soft Error Rate in VLSI Circuits , 1982, IEEE Journal of Solid-State Circuits.

[8]  P. Chatterjee,et al.  Enhanced Performance 4KX1 High Speed SRAM Using Optically Defined Submicron Devices in Selected Circuits , 1981, 1981 Symposium on VLSI Technology. Digest of Technical Papers.

[9]  H. Shichijo.  A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI , 1981, 1981 International Electron Devices Meeting.

[10]  W.W. Walker,et al.  Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor , 1980, IEEE Transactions on Electron Devices.

[11]  P.I. Suciu,et al.  High-speed NMOS circuits made with X-ray lithography and reactive sputter etching , 1980, IEEE Electron Device Letters.

[12]  C. Sodini,et al.  The junction MOS (JMOS) transistor - A high speed transistor for VLSI , 1980, 1980 International Electron Devices Meeting.

[13]  K. Terada,et al.  A New Method to Determine Effective MOSFET Channel Length , 1979 .

[14]  Richard C. Jaeger,et al.  Temperature dependent threshold behavior of depletion mode MOSFETs: Characterization and simulation☆ , 1979 .

[15]  R.H. Dennard,et al.  1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications , 1979, IEEE Transactions on Electron Devices.

[16]  J. T. Clemens,et al.  Characterization of the electron mobility in the inverted <100> Si surface , 1979, 1979 International Electron Devices Meeting.

[17]  V. L. Rideout,et al.  Very small MOSFET's for low-temperature operation , 1977, IEEE Transactions on Electron Devices.

[18]  R.W. Keyes,et al.  Physical limits in digital electronics , 1975, Proceedings of the IEEE.

[19]  K. Steinhubl.  Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[20]  A. S. Grove,et al.  Temperature dependence of MOS transistor characteristics below saturation , 1966 .