Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoC Neyaz Khan

Virtually all modern SoC designs today are mixed-signal in nature. Most systems have to interface their millions of gates, DSPs, memories, and processors to the real world through a display, an antenna, a sensor, a cable or an RF interface. The already complex task of functional verification at the SoC level is getting harder and more time consuming. Up until recently, mixed-signal designs could be decomposed into separate analog and digital functions. Traditionally, digital verification engineers have made assumptions and approximations about the analog components and likewise, the analog designers have made assumptions about the digital behavior. Present day mixed-signal designs have multiple feedback loops with complex system-level interaction between digital and analog components, which is often a rich source of errors. There is a need for an integrated mixed-signal simulation and verification strategy and methodology that can be used to extend advanced verification techniques from the digital verification realm to analog components without compromising speeds needed to verify digital components while preserving the accuracy needed to model and verify analog components. On an orthogonal plane, the mandate for power reduction is being pursued at every level of IC design for more energy efficient systems. For static power reduction, IC designers are widely deploying power shut-off (PSO) techniques in the design. In applications where PSO is not applicable, power management is often achieved by dynamically scaling the operating frequency and voltage of the target design in real time – a technique know as DVFS (Dynamic Voltage and Frequency Scaling). The verification of DVFS is often a very difficult and delicate task that involves tremendous interaction between the digital and the analog domains. This further increases the complexity of functional verification, which was already a bottle neck, and now becomes even more complex and time-consuming task at the SoC level. This paper will introduce Digital-centric Mixed Signal (DMS) Verification methodology and provide an overview of how it can enable high performance SoC-level mixed signal verification at digital speeds using Real Number Modeling (RNM) of analog components. Dynamic Power management techniques will be examined in detail. DMS methodology will be applied to an SoC example running Adaptive DVFS as a case study.