Delay Test and Small-Delay Defects

As technology scales downwards, new challenges are emerging for test engineers. The deep-submicron effects are becoming more prominent with shrinking technology, thereby increasing the probability of timing-related defects [22, 24]. As a result, the stuck-at and I DDQ tests alone cannot ensure high quality level of chips, and at-speed test is needed to cover these timing-related defects. In the past, functional patterns were used for at-speed test. However, functional test generation is difficult and time-consuming for large complex designs. As mentioned previously, functional patterns also have pattern count and coverage issues. A cost-effective alternative are the scan-based structural tests generated by at-speed automatic test pattern generators. The transition fault model and path-delay fault model together provide relatively good coverage for delay-induced defects [5, 13, 26, 29].

[1]  Srikanth Venkataraman,et al.  Evaluation of the quality of N-detect scan ATPG patterns on a processor , 2004 .

[2]  Jing Wang,et al.  K longest paths per gate (KLPG) test generation for scan-based sequential circuits , 2004 .

[3]  N. Ahmed,et al.  A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[4]  Kwang-Ting Cheng,et al.  New challenges in delay testing of nanometer, multigigahertz designs , 2004, IEEE Design & Test of Computers.

[5]  Srinivas Patil,et al.  On broad-side delay test , 1994, Proceedings of IEEE VLSI Test Symposium.

[6]  Melvin A. Breuer,et al.  Process variations and their impact on circuit operation , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[7]  B.I. Dervisoglu,et al.  DESIGN FOR TESTABILITY USING SCANPATH TECHNIQUES FOR PATH-DELAY TEST AND MEASUREMENT , 1991, 1991, Proceedings. International Test Conference.

[8]  Kwang-Ting Cheng,et al.  False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation , 2002, DAC '02.

[9]  Irith Pomeranz,et al.  Selecting High-Quality Delay Tests for Manufacturing Test and Debug , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[10]  M. Ray Mercer,et al.  Statistical delay fault coverage and defect level for delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[11]  Melvin A. Breuer,et al.  Analytic models for crosstalk delay and pulse analysis under non-ideal inputs , 1997, Proceedings International Test Conference 1997.

[12]  Mark Mohammad Tehranipoor,et al.  Test-Pattern Grading and Pattern Selection for Small-Delay Defects , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[13]  Kwang-Ting Cheng,et al.  Transition fault testing for sequential circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Yu Huang.  On N-detect pattern set optimization , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[15]  Mark Mohammad Tehranipoor,et al.  Timing-based delay test for screening small delay defects , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[16]  Narendra Devta-Prasanna,et al.  Effective and Efficient Test Pattern Generation for Small Delay Defect , 2009, 2009 27th IEEE VLSI Test Symposium.

[17]  Lalit M. Patnaik,et al.  Line coverage of path delay faults , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Jacob Savir,et al.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[19]  Michael S. Hsiao,et al.  ALAPTF: a new transition fault model and the ATPG algorithm , 2004 .

[20]  Mark Mohammad Tehranipoor,et al.  Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects , 2008, 2008 IEEE International Test Conference.

[21]  Janusz Rajski,et al.  High-frequency, at-speed scan testing , 2003, IEEE Design & Test of Computers.

[22]  Jan M. Rabaey,et al.  Digital integrated circuits: a design perspective / Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic , 2003 .

[23]  Mark Mohammad Tehranipoor,et al.  Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths , 2009, 2009 27th IEEE VLSI Test Symposium.