Flexible Wormhole-Switched Network-on-chip with Two-Level Priority Data Delivery Service

A synchronous network-on-chip using wormhole packet switch- ing and supporting guaranteed-completion best-effort with low-priority (LP) and high-priority (HP) wormhole packet delivery service is presented in this paper. Both our proposed LP and HP message services deliver a good quality of service in term of lossless packet completion and in-order message data delivery. However, the LP message service does not guarantee minimal completion bound. The HP packets will absolutely use 100% bandwidth of their reserved links if the HP packets are injected from the source node with maximum injection. Hence, the service are suitable for small size messages (less than hundred bytes). Otherwise the other HP and LP messages, which require also the links, will experience relatively high latency depending on the size of the HP message. The LP packets are routed using a minimal adaptive routing, while the HP packets are routed using a non-minimal adaptive routing algorithm. Therefore, an additional 3-bit field, identifying the packet type, is introduced in their packet headers to classify and to determine the type of service committed to the packet. Our NoC prototypes have been also synthesized using a 180-nm CMOS standard-cell technology to evaluate the cost of implementing the combination of both services.

[1]  Brent Nelson,et al.  PNoC: a flexible circuit-switched NoC for FPGA-based systems , 2006 .

[2]  Axel Jantsch,et al.  Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Alain Greiner,et al.  A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[4]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[5]  Akif Ali,et al.  Near-optimal worst-case throughput routing for two-dimensional mesh networks , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[6]  Axel Jantsch,et al.  Networks on chip , 2003 .

[7]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.

[8]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[9]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[10]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[11]  Philippe Martin Design of a virtual component neutral network-on-chip transaction layer , 2005, Design, Automation and Test in Europe.

[12]  Jin Seek Choi,et al.  Delay performance of an input queueing packet switch with two priority classes , 1998 .

[13]  Jens Sparsø,et al.  Implementation of guaranteed services in the MANGO clockless network-on-chip , 2006 .

[14]  Chita R. Das,et al.  A low latency router supporting adaptivity for on-chip interconnects , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[15]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1992, ISCA '92.

[16]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[17]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[18]  Fabien Clermidy,et al.  An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[19]  Jari Nurmi,et al.  Interconnect IP node for future system-on-chip designs , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

[20]  Jörg Henkel,et al.  A design methodology for application-specific networks-on-chip , 2006, TECS.

[21]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[22]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[23]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[24]  Lionel M. Ni,et al.  Adaptive routing in mesh-connected networks , 1992, [1992] Proceedings of the 12th International Conference on Distributed Computing Systems.

[25]  Luciano Lavagno,et al.  Asynchronous on-chip networks , 2005 .

[26]  Luca Benini,et al.  Network-on-chip architectures and design methods , 2005 .

[27]  Vincenzo Catania,et al.  Neighbors-on-Path: A New Selection Strategy for On-Chip Networks , 2006, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia.

[28]  Rudy Lauwereins,et al.  Topology adaptive network-on-chip design and implementation , 2005 .

[29]  Manfred Glesner,et al.  Deadlock-free routing and component placement for irregular mesh-based networks-on-chip , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[30]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[31]  Drew Wingard MicroNetwork-based integration for SOCs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).