Automatic Construction of On-line Checking Circuits Based on Finite Automata

In this paper, the approach to the automatic development of checking circuits for unit implemented in FPGA is described. The checking circuit, also denoted as online checker, introduces fault tolerance aspects to the unit. It provides the information about correctness of the unit output. Checkers are constructed from models inferred by active automata learning which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. A platform for automatic construction of online checkers has been designed and implemented. The experimental part of the paper proves that it is possible to automatically generate the model for the online checker which describes the basic behaviour of the checked component. The obtained checker is up to six times smaller than the original component.

[1]  Roland Groz,et al.  Inferring Mealy Machines , 2009, FM.

[2]  Sunil P. Khatri,et al.  A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements , 2008, 2008 Design, Automation and Test in Europe.

[3]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[4]  Zdenek Kotásek,et al.  Checker Design for On-line Testing of Xilinx FPGA Communication Protocols , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[5]  Peter Hazucha,et al.  Characterization of soft errors caused by single event upsets in CMOS processes , 2004, IEEE Transactions on Dependable and Secure Computing.

[6]  R. Richter,et al.  Use of Triple Modular Redundancy (TMR) technology in FPGAs for the reduction of faults due to radiation in the readout of the ATLAS monitored drift tube (MDT) chambers , 2010, IEEE Nuclear Science Symposuim & Medical Imaging Conference.

[7]  Xiaowei Li,et al.  SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  A.T. Abdel-Hamid,et al.  A tool converting finite state machine to VHDL , 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).

[9]  Bernhard Steffen,et al.  Active Automata Learning: From DFAs to Interface Programs and Beyond , 2012, ICGI.

[10]  Dana Angluin,et al.  Learning Regular Sets from Queries and Counterexamples , 1987, Inf. Comput..

[11]  Tiziana Margaria,et al.  Automated Learning Setups in Automata Learning , 2012, ISoLA.

[12]  T. Margaria,et al.  Efficient Regression Testing of CTI-Systems : Testing a complex Call-Center Solution , 2001 .

[13]  Bernhard Steffen,et al.  Introduction to Active Automata Learning from a Practical Perspective , 2011, SFM.

[14]  Anil Nerode,et al.  Automata theory and its applications , 2001 .

[15]  Manfred Broy,et al.  Model-Based Testing of Reactive Systems, Advanced Lectures [The volume is the outcome of a research seminar that was held in Schloss Dagstuhl in January 2004] , 2005, Model-Based Testing of Reactive Systems.

[16]  Martin Straka,et al.  Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration , 2010, DSD 2010.

[17]  Bengt Jonsson,et al.  Inferring Semantic Interfaces of Data Structures , 2012, ISoLA.

[18]  T. Kanade.  Model-Based Testing of Reactive Systems , 2005 .

[19]  AngluinDana.  Learning regular sets from queries and counterexamples , 1987 .

[20]  Jakub Podivinsky,et al.  A Complex Control System for Testing Fault-Tolerance Methodologies , 2014 .

[21]  Tiziana Margaria,et al.  Efficient test-based model generation for legacy reactive systems , 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

[22]  Edward J. McCluskey,et al.  Error detection by selective procedure call duplication for low energy consumption , 2002, IEEE Trans. Reliab..