The POTATO chip architecture: a study in tradeoffs for signal processing chip design

The authors describe an example signal-processing design which illustrates partitioning, performance, cost, and fault-tolerance tradeoffs. They focus on high-performance multiplication using the power-of-two number representation as implemented in the POTATO (power of two arithmetic time-optimized) chip architecture. The implementation is compared to more conventional designs, and performance estimates are given. It is concluded that the design compares favourably to more conventional implementations.<<ETX>>

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