EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction

As the technology node continuously scales down, layout-dependent effects (LDEs) have been significantly affecting the threshold voltage and mobility of MOSFET transistors and then, in turn, the performance of analog integrated circuits. In this paper, we propose an LDE optimization methodology based on the evolutionary algorithm, which aims to protect analog circuits from the LDE-induced circuit performance degradation. With the aid of a fast analog layout retargeting scheme, our proposed optimization can evaluate the circuit performance with the consideration of detailed physical layouts, tune the device placement and transistor finger number, and modify the layout patterns for the LDE-aware circuit performance preservation. To accelerate the physical layout synthesis, our new retargeting process supports general device abstraction. The experimental results show that our proposed methodology can more effectively preserve analog and even RF circuit performance with higher efficiency than the alternative approaches.

[1]  Behjat Forouzandeh,et al.  Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits , 2016, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[2]  Mohamed Dessouky,et al.  Layout Dependent Effects mitigation in current mirrors , 2016, 2016 Fourth International Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC).

[3]  Yu Zhang,et al.  Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[4]  Lihong Zhang,et al.  Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[5]  Lihong Zhang,et al.  MEMS piezoelectric energy harvester design and optimization based on Genetic Algorithm , 2016, 2016 IEEE International Ultrasonics Symposium (IUS).

[6]  Zuochang Ye,et al.  A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Jyh-Chyurn Guo,et al.  The impact of layout dependent effects on mobility and flicker noise in nanoscale multifinger nMOSFETs for RF and analog design , 2016, 2016 IEEE MTT-S International Microwave Symposium (IMS).

[8]  Zuochang Ye,et al.  A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect , 2012, IEEE Transactions on Electron Devices.

[9]  Sudeb Dasgupta,et al.  Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits , 2016, IEEE Transactions on Electron Devices.

[10]  Arvind Kumar Sharma,et al.  Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies , 2015, 2015 19th International Symposium on VLSI Design and Test.

[11]  Sachin S. Sapatnekar,et al.  The impact of shallow trench isolation effects on circuit performance , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Yingtao Jiang,et al.  A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs , 2005, Int. J. Circuit Theory Appl..

[13]  M. Rafik,et al.  Layout Dependent Effect: Impact on device performance and reliability in recent CMOS nodes , 2016, 2016 IEEE International Integrated Reliability Workshop (IIRW).

[14]  J. Ju,et al.  Characterization FinFET device layout dependent effect , 2016, China Semiconductor Technology International Conference.

[15]  Yu Zhang,et al.  CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[16]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[17]  Yao-Wen Chang,et al.  Layout-Dependent Effects-Aware Analytical Analog Placement , 2016, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Rashad Ramzan,et al.  Design layout optimization in the presence of proximity-dependent stress effects , 2014, 2014 IEEE International Conference on IC Design & Technology.

[19]  Lihong Zhang,et al.  Lithography-Aware Analog Layout Retargeting , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Chien-Hung Chen,et al.  Fast analog layout prototyping for nanometer design migration , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).