The future of high-performance CMOS: Trends and requirements

Intrinsic MOSFET time delay is examined as a function of scaling of high-performance CMOS technology. An analytical expression is used to calculate delay from physically meaningful transistor characteristics, which are either obtained from the literature or projected forward. The key performance parameter is the calculated virtual-source carrier velocity in the channel which is shown to be responsible for the historical decrease of transistor delay with scaling. Forward projection of transistor delay is based on an optimistic scaling scenario with realistic assumptions about device geometry, electrostatic integrity, and parasitics. It is shown that from the 32-nm CMOS generation onward the intrinsic transistor performance will not improve unless parasitic capacitances are significantly reduced. Finally, characteristics of performance scaling under localized circuit power density constraints are examined.

[1]  T. Schulz,et al.  An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits , 2007, 2007 IEEE International Electron Devices Meeting.

[2]  J. Sudijono,et al.  High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology , 2007, 2007 IEEE Symposium on VLSI Technology.

[3]  E. Cohen,et al.  Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements , 2007, IEEE Journal of Solid-State Circuits.

[4]  Ali Khaki-Firooz,et al.  Transport enhancement techniques for nanoscale MOSFETs , 2008 .

[5]  S. Narasimha,et al.  High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography , 2006, 2006 International Electron Devices Meeting.

[6]  E.J. Nowak,et al.  The effective drive current in CMOS inverters , 2002, Digest. International Electron Devices Meeting,.

[7]  S. Takahashi,et al.  A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL , 2006, 2006 International Electron Devices Meeting.

[8]  Mark S. Lundstrom,et al.  Quantum mechanical analysis of channel access geometry and series resistance in nanoscale transistors , 2004 .

[9]  H.J. Tao,et al.  45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application , 2007, 2007 IEEE International Electron Devices Meeting.

[10]  E. Nowak,et al.  High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .

[11]  P. Bai,et al.  An advanced low power, high performance, strained channel 65nm technology , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[12]  D.A. Antoniadis,et al.  MOSFET Performance Scaling—Part II: Future Directions , 2008, IEEE Transactions on Electron Devices.

[13]  S. Narendra,et al.  Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors , 2003 .

[14]  Wilfried Haensch,et al.  Optimizing CMOS technology for maximum performance , 2006, IBM J. Res. Dev..

[15]  Vivek De,et al.  A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[16]  Kuan-Lun Cheng.  A Highly Scaled, HighPerformance 45nmBulkLogic CMOS Technology with0.242 , 2007 .

[17]  K. Saraswat,et al.  Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[18]  Sanu Mathew,et al.  A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit , 2007, IEEE J. Solid State Circuits.

[19]  Jason C. S. Woo,et al.  Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part I: , 2002 .

[20]  David J. Frank,et al.  Power-constrained CMOS scaling limits , 2002, IBM J. Res. Dev..

[21]  Syed Muhammad Zain Zafar,et al.  High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing , 2007, 2007 IEEE Symposium on VLSI Technology.

[22]  J. Woo,et al.  Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation , 2002 .

[23]  D.A. Antoniadis,et al.  MOSFET Performance Scaling—Part I: Historical Trends , 2008, IEEE Transactions on Electron Devices.

[24]  D.A. Antoniadis,et al.  Transistor Performance Scaling: The Role of Virtual Source Velocity and Its Mobility Dependence , 2006, 2006 International Electron Devices Meeting.

[25]  S. Asano,et al.  The design and implementation of a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[26]  Mark S. Lundstrom.  Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[27]  Anantha Chandrakasan,et al.  Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[28]  G.T. Wright.  A simple and continuous MOSFET model , 1985, IEEE Transactions on Electron Devices.

[29]  Gaurav Mittal,et al.  Design of the Power6 Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[30]  Osama M. Nayfeh,et al.  Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations , 2006, IBM J. Res. Dev..

[31]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[32]  R. Jammy,et al.  High Performance pMOSFETs Using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial Strain for 22 nm Technology Node , 2007, 2007 IEEE International Electron Devices Meeting.

[33]  E. Yoshida,et al.  Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS , 2006, 2006 International Electron Devices Meeting.