Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation

This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest.

[1]  N. Ranganathan,et al.  A linear programming formulation for security-aware gate sizing , 2008, GLSVLSI '08.

[2]  H. Zhou,et al.  Gate Sizing by Lagrangian Relaxation Revisited , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Jiang Hu,et al.  A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Lawrence T. Pileggi,et al.  The Elmore Delay as a Bound for RC Trees with Generalized Input Signals , 1995, 32nd Design Automation Conference.

[5]  Sung-Mo Kang,et al.  An exact solution to the transistor sizing problem for CMOS circuits using convex optimization , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Ruchir Puri,et al.  Fast and accurate wire delay estimation for physical synthesis of large ASICs , 2002, GLSVLSI '02.

[7]  Jiang Hu,et al.  Gate sizing and device technology selection algorithms for high-performance industrial designs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Hiran Tennakoon,et al.  Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[9]  Hiran Tennakoon,et al.  Efficient and accurate gate sizing with piecewise convex delay models , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[10]  Charlie Chung-Ping Chen,et al.  Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation , 2005, ASP-DAC.

[11]  Hiran Tennakoon,et al.  Power reduction via near-optimal library-based cell-size selection , 2011, 2011 Design, Automation & Test in Europe.

[12]  Charlie Chung-Ping Chen,et al.  Fast and effective gate-sizing with multiple-V/sub t/ assignment using generalized Lagrangian relaxation , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[13]  Steven M. Burns,et al.  An improved benchmark suite for the ISPD-2013 discrete cell sizing contest , 2013, ISPD '13.

[14]  Wing Ning Li,et al.  Strongly NP-hard discrete gate sizing problems , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[15]  Umesh V. Vazirani,et al.  "Go with the winners" algorithms , 1994, Proceedings 35th Annual Symposium on Foundations of Computer Science.

[16]  Shiyan Hu,et al.  Gate Sizing for Cell-Library-Based Designs , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  David G. Chinnery,et al.  Linear programming for sizing, Vth and Vdd assignment , 2005, ISLPED '05.

[18]  Guilherme Flach,et al.  Gate sizing using geometric programming , 2011, 2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS).

[19]  Jin Hu,et al.  Sensitivity-guided metaheuristics for accurate discrete gate sizing , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[20]  Lawrence T. Pileggi,et al.  Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Marcelo de Oliveira Johann,et al.  Fast and efficient Lagrangian Relaxation-based Discrete Gate Sizing , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[22]  Steven M. Burns,et al.  The ISPD-2012 discrete cell sizing contest and benchmark suite , 2012, ISPD '12.

[23]  Guilherme Flach,et al.  Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[24]  Guilherme Flach,et al.  Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities , 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[25]  Carl Sechen,et al.  Post-synthesis leakage power minimization , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[26]  Martin D. F. Wong,et al.  Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[27]  Li Li,et al.  An efficient algorithm for library-based cell-type selection in high-performance low-power designs , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).