Removing overhead from high-level interfaces

Hardware modules would be much easier to reuse if they supported generic flexible high-level interfaces. However, these interfaces are rarely used since they lead to timing and area overheads compared to a customized design. This paper describes a reachability analysis framework that identifies over-provisioning in instances of flexible design, and offers a technique for annotating this information so that modern synthesis tools can remove most of the overhead. Results are demonstrated on a variety of flexible structures, including functional blocks, programmable state machines, and latency-insensitive interfaces.

[1]  Mark Horowitz,et al.  Intermediate representations for controllers in chip generators , 2011, 2011 Design, Automation & Test in Europe.

[2]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, & Tools with Gradiance , 2007 .

[3]  David L. Dill,et al.  The Murphi Verification System , 1996, CAV.

[4]  Christoforos E. Kozyrakis,et al.  A memory system design framework: creating smart memories , 2009, ISCA '09.

[5]  Rishiyur S. Nikhil,et al.  Bluespec System Verilog: efficient, correct RTL from high level specifications , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..

[6]  Alan Mishchenko,et al.  Scalable and scalably-verifiable sequential synthesis , 2008, ICCAD 2008.

[7]  Markus Wedler,et al.  Structural FSM traversal , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Enrico Macii,et al.  Algorithms for Approximate FSM Traversal , 1993, 30th ACM/IEEE Design Automation Conference.