A high-precision VLSI winner-take-all circuit for self-organizing neural networks

The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2- mu m CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks. >

[1]  Yannis Tsividis,et al.  A reconfigurable VLSI neural network , 1992 .

[2]  Richard F. Lyon,et al.  An analog electronic cochlea , 1988, IEEE Trans. Acoust. Speech Signal Process..

[3]  John Lazzaro,et al.  Winner-Take-All Networks of O(N) Complexity , 1988, NIPS.

[4]  Yoh-Han Pao,et al.  Adaptive pattern recognition and neural networks , 1989 .

[5]  Bing J. Sheu,et al.  An analog neural network processor for self-organizing mapping , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[6]  Rodney M. Goodman,et al.  A real-time neural system for color constancy , 1991, IEEE Trans. Neural Networks.

[7]  Bing J. Sheu,et al.  An MOS transistor charge model for VLSI design , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Teuvo Kohonen,et al.  The self-organizing map , 1990 .

[9]  Judith E. Dayhoff,et al.  Neural Network Architectures: An Introduction , 1989 .

[10]  Ralph Etienne-Cummings,et al.  An analog neural computer with modular architecture for real-time dynamic computations , 1992 .

[11]  Ezz I. El-Masry,et al.  Feedforward associative memory switched-capacitor artificial neural networks , 1991 .

[12]  G. Lewicki.  FORESIGHT: a fast turn-around and low cost ASIC prototyping alternative , 1990, Third Annual IEEE Proceedings on ASIC Seminar and Exhibit.

[13]  Teuvo Kohonen,et al.  Self-Organization and Associative Memory , 1988 .

[14]  Tobi Delbrück,et al.  Cooperative Stereo Matching Using Static and Dynamic Image Features , 1989, Analog VLSI Implementation of Neural Systems.

[15]  Bing J. Sheu,et al.  BSIM: Berkeley short-channel IGFET model for MOS transistors , 1987 .

[16]  Jin Luo,et al.  Real-Time Computer Vision and Robotics Using Analog VLSI Circuits , 1989, NIPS.

[17]  Stephen Grossberg,et al.  Competitive Learning: From Interactive Activation to Adaptive Resonance , 1987, Cogn. Sci..

[18]  C. Tomovich,et al.  MOSIS - A gateway to silicon , 1988, IEEE Circuits and Devices Magazine.

[19]  Edgar Sánchez-Sinencio,et al.  A modular CMOS design of a Hamming network , 1992, IEEE Trans. Neural Networks.

[20]  John Lazzaro,et al.  Analog VLSI model of binaural hearing , 1991, IEEE Trans. Neural Networks.

[21]  Lawrence D. Jackel,et al.  Application of the ANNA neural network chip to high-speed character recognition , 1992, IEEE Trans. Neural Networks.

[22]  Richard P. Lippmann,et al.  An introduction to computing with neural nets , 1987 .

[23]  Oscal T.-C. Chen,et al.  A VLSI neural processor for image data compression using self-organization networks , 1992, IEEE Trans. Neural Networks.

[24]  Andreas G. Andreou,et al.  Current-mode subthreshold MOS circuits for analog VLSI neural systems , 1991, IEEE Trans. Neural Networks.