Control speculation in multithreaded processors through dynamic loop detection
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[1] Gurindar S. Sohi,et al. Multiscalar processors , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.
[2] Gurindar S. Sohi,et al. The Expandable Split Window Paradigm for Exploiting Fine-grain Parallelism , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.
[3] David W. Wall,et al. Limits of instruction-level parallelism , 1991, ASPLOS IV.
[4] Quinn Jacobson,et al. Control flow speculation in multiscalar processors , 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.
[5] Vojin G. Oklobdzija,et al. Multithreaded Decoupled Architecture , 1995, Int. J. High Speed Comput..
[6] Yale N. Patt,et al. A Comparison Of Dynamic Branch Predictors That Use Two Levels Of Branch History , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.
[7] Kevin O'Brien,et al. Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grained multithreading , 1995, PACT.
[8] Jenn-Yuan Tsai,et al. The superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation , 1996, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique.
[9] Monica S. Lam,et al. Limits of control flow on parallelism , 1992, ISCA '92.
[10] Makoto Kobayashi. Dynamic Characteristics of Loops , 1984, IEEE Transactions on Computers.
[11] James E. Smith,et al. A study of branch prediction strategies , 1981, ISCA '98.
[12] José González,et al. Speculative execution via address prediction and data prefetching , 1997, ICS '97.