Die-level leakage power analysis of FinFET circuits considering process variations

In the recent past, FinFETs have been touted as promising alternatives to planar CMOS owing to their superior short-channel characteristics. However, due to lithographic constraints, they are likely to suffer from the effects of process variations, which are manifested as large spreads in leakage current and delay in combinational logic circuits. In this work, we model the leakage probability density function (pdf) in shorted-gate (SG), independent-gate (IG)/low-power (LP), and mixed-terminal (MT) FinFET standard logic cells, and examine the leakage tradeoffs in benchmark circuits synthesized using combinations of SG-, LP-, and MT-mode logic cells under the effect of process variations. Using quasi-Monte Carlo mixed-mode device simulations in Sentaurus TCAD, we develop simple macromodels to capture the physical effects influencing the leakage spread in SG- and IG-mode FinFET devices, and extend it to stacked devices in NAND/NOR gates. We also implement a methodology to obtain the overall leakage current distribution for large circuits (synthesized using SG/LP/MT-mode logic cells) using Latin hypercube sampling, considering spatial correlation on a quad-tree based grid. Results indicate that, starting from a 100% SG-mode circuit, the leakage spread/yield point can be improved considerably by suitably introducing LP-mode and MT-mode gates at iso-delay. We also show that increasing the fraction of LP/MT-mode gates (to reduce the mean and variance in leakage) in an SG-mode circuit, by permitting a delay slack, yields diminishing returns. Mixing LP- and MT-mode gates with SG-mode gates appears to be a promising synthesis strategy that can leverage the leakage tradeoffs offered by FinFET standard cells.

[1]  Jie Gu,et al.  Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Kaushik Roy,et al.  The effect of process variation on device temperature in FinFET circuits , 2007, ICCAD 2007.

[3]  D. Sylvester,et al.  Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[4]  Jinjun Xiong,et al.  Robust Extraction of Spatial Correlation , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  David Blaauw,et al.  Statistical timing analysis for intra-die process variations with spatial correlations , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[6]  Walter S. Scott,et al.  Magic: A VLSI Layout System , 1984, 21st Design Automation Conference Proceedings.

[7]  Yu Cao,et al.  Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[8]  Rob A. Rutenbar,et al.  From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[9]  Soha Hassoun,et al.  Gate sizing: finFETs vs 32nm bulk MOSFETs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  E.J. Nowak,et al.  Turning silicon on its edge [double gate CMOS/FinFET technology] , 2004, IEEE Circuits and Devices Magazine.

[11]  Kaushik Roy,et al.  Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[12]  Kaushik Roy,et al.  A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Niraj K. Jha,et al.  Pragmatic design of gated-diode FinFET DRAMs , 2009, 2009 IEEE International Conference on Computer Design.

[14]  Y. Taur,et al.  A continuous, analytic drain-current model for DG MOSFETs , 2004 .

[15]  C. Hu,et al.  BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design , 2007, 2007 IEEE Symposium on VLSI Technology.

[16]  A. Kumar,et al.  Low voltage and performance tunable CMOS circuit design using independently driven double gate MOSFETs , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

[17]  N. Higham.  Computing the nearest correlation matrix—a problem from finance , 2002 .

[18]  A. Sangiovanni-Vincentelli,et al.  The TimberWolf placement and routing package , 1985, IEEE Journal of Solid-State Circuits.

[19]  Anish Muttreja,et al.  CMOS logic design with independent-gate FinFETs , 2007, 2007 25th International Conference on Computer Design.

[20]  Kaushik Roy,et al.  The effect of process variation on device temperature in finFET circuits , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[21]  L. Mathew,et al.  Physical insights regarding design and performance of independent-gate FinFETs , 2005, IEEE Transactions on Electron Devices.

[22]  Anish Muttreja,et al.  Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[23]  Sachin S. Sapatnekar,et al.  Full-chip analysis of leakage power under process variations, including spatial correlations , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[24]  Jinjun Xiong,et al.  Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  V. Kursun,et al.  High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise , 2007, 2007 Internatonal Conference on Microelectronics.

[26]  Massimo Alioto,et al.  Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction , 2009, PATMOS.

[27]  G. O. Workman,et al.  A process/physics-based compact model for nonclassical CMOS device and circuit design , 2004 .

[28]  Yuan Xie,et al.  Power optimization for FinFET-based circuits using genetic algorithms , 2008, 2008 IEEE International SOC Conference.

[29]  C. Tretz,et al.  Novel high-density low-power logic circuit techniques using DG devices , 2005, IEEE Transactions on Electron Devices.

[30]  J. Bokor,et al.  Sensitivity of double-gate and FinFETDevices to process variations , 2003 .