A method of static compaction of test stimuli

Large numbers of test stimuli impact on test application time and cost of test application. Hence there is the need to keep numbers of test stimuli low while maintaining as high fault coverage as possible. In this paper, static compaction of test stimuli is seen as a minimization problem. The task of static compaction of a set of test stimuli has been formulated as a minimum covering problem. Based on the concept of minimization, a method of static compaction has been developed. Results of experiments conducted to evaluate the method are also presented. The method achieved a significant compaction of sets of test stimuli that had previously been compacted by means of a test generation algorithm that features dynamic compaction.

[1]  Michael S. Hsiao,et al.  Fast algorithms for static compaction of sequential circuit test vectors , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[2]  Michael S. Hsiao,et al.  Partitioning and reordering techniques for static test sequence compaction of sequential circuits , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[3]  Michael S. Hsiao,et al.  Fast Static Compaction Algorithms for Sequential Circuit Test Vectors , 1999, IEEE Trans. Computers.

[4]  Hiroshi Takahashi,et al.  Diagnosing Delay Faults in Combinational Circuits under the Ambiguous Delay Model , 1999 .

[5]  Janak H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[6]  Hiroshi Takahashi,et al.  Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays , 1998 .

[7]  Michael S. Hsiao,et al.  State relaxation based subsequence removal for fast static compaction in sequential circuits , 1998, Proceedings Design, Automation and Test in Europe.

[8]  Kewal K. Saluja,et al.  On test pattern compaction using random pattern fault simulation , 1998, Proceedings Eleventh International Conference on VLSI Design.

[9]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[10]  Hiroshi Takahashi,et al.  Multiple fault diagnosis by sensitizing input pairs , 1995, IEEE Design & Test of Computers.

[11]  Irith Pomeranz,et al.  On test compaction objectives for combinational and sequential circuits , 1998, Proceedings Eleventh International Conference on VLSI Design.