An Efficient Two-Dimensional Layout Compaction Algorithm

A new heuristic two-dimensional symbolic layout-compaction approach is developed. After conventional one-dimensional compaction steps, all the components on the critical paths that define the height or width of the given layout are found and rearranged to reduce the layout size. During this process, constraints in both x and y directions are considered and pitch-matching of ports for hierarchical compaction can be achieved to reduce the amount of the design data. This approach generated the smallest area for several examples we have tried when compared with other published results. The expected run time can be bounded by O(T/sub 1/, where T/sub 1/ is the run time of a typical one-dimensional compactor.