High speed pipelined multiplier architecture is proposed in this paper. The pipelined architecture consists of 3 stages. 1st stage consists of the 4 - bit Vedic Multiplication unit. 2nd stage consists of partial products and carry. 3rd stage consists of adders and the result of the multiplication. This paper presents the efficiency of Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of partial products and eliminates unwanted multiplication steps. The proposed algorithm is modeled using Verilog, a hardware description language. It is found that 11 logic cells are required to build nibble multiplier. The propagation time of the proposed architecture is found to be 4.585ns. Implementation has been done for the Xilinx FPGA device, Spartan-3E. The results shows that multiplier implemented using Vedic multiplication is efficient in terms of area and speed compared to its implementation using Array and Booth multiplier architectures.
[1]
M. Ramalatha,et al.
High speed energy efficient ALU design using Vedic multiplication techniques
,
2009,
2009 International Conference on Advances in Computational Tools for Engineering Applications.
[2]
Richard Conway,et al.
Lifting scheme discrete Wavelet Transform using Vertical and Crosswise multipliers
,
2008
.
[3]
H. H. Guild.
Fully iterative fast array for binary multiplication and addition
,
1969
.
[4]
Hamid R. Arabnia,et al.
Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture
,
2005,
AMCS.
[5]
M. Morris Mano,et al.
Computer system architecture
,
1982
.
[6]
Harpreet S. Dhillon,et al.
A Reduced-Bit Multiplication Algorithm for Digital Arithmetic
,
2008
.
[7]
Milos D. Ercegovac,et al.
High-performance left-to-right array multiplier design
,
2003,
Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.