Design and Implementation of DSP algorithms for 100 Gbps Coherent Optical-OFDM (CO-OFDM) Systems

Multi-band Coherent Optical OFDM (MB CO-OFDM) is widely predicted to be one of the technologies which will empower 100 Gigabit Ethernet (100GbE) networks. CO-OFDM uses coherent technology and advanced digital signal processing (DSP) to achieve net data rate of 10 Gbps in a single band. This strict throughput requirement puts a constraint on the kind of signal processing algorithms and architectures used for building the system. In this paper, a scalable parallel architecture using radix-2$^{2}$ for IFFT is proposed. The second proposal consists of a scalable parallel timing synchronization algorithm which can support very high input rates at the receiver. MOPS count as well as area versus throughput for the synchronization algorithm are provided for the OFDM transceiver to show the improvements due to proposed architecture. Architecture exploration is done using a leading-edge high-level synthesis (HLS) tool.

[1]  Jae Hong Lee,et al.  An Initial Timing Offset Estimation Method for OFDM Systems in Rayleigh Fading Channel , 2006, IEEE Vehicular Technology Conference.

[2]  C.-C. Jay Kuo,et al.  Synchronization Techniques for Orthogonal Frequency Division Multiple Access (OFDMA): A Tutorial Review , 2007, Proceedings of the IEEE.

[3]  Hang Liu,et al.  A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[4]  Khaled Ben Letaief,et al.  A robust timing and frequency synchronization for OFDM systems , 2003, IEEE Trans. Wirel. Commun..

[5]  J. D'Ambrosia.  100 gigabit Ethernet and beyond [Commentary] , 2010 .

[6]  Mats Torkelson,et al.  A new approach to pipeline FFT processor , 1996, Proceedings of International Conference on Parallel Processing.

[7]  Jesús Grajal,et al.  Pipelined Radix-$2^{k}$ Feedforward FFT Architectures , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[9]  Sangsung Choi,et al.  A high-speed, low-complexity radix-2/sup 4/ FFT processor for MB-OFDM UWB systems , 2006, 2006 IEEE International Symposium on Circuits and Systems.