Design Automation and Case Studies

All the architectures proposed in the previous chapters have been realized using the bit-sliced design paradigm. The architectures are very regular in their structures, thereby serving as a motivation to automate the generation of the arithmetic circuit descriptions for the target FPGA platform. In this chapter, we will introduce the proposed CAD tool for design automation named FlexiCore. We also present two relevant case studies comprising of multiple modules, whose HDL and placement constraints can be generated using FlexiCore.

[1]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[2]  Javier Hormigo,et al.  Self-Reconfigurable Constant Multiplier for FPGA , 2013, TRETS.

[3]  Abbes Amira,et al.  An FPGA based parameterizable system for matrix product implementation , 2002, IEEE Workshop on Signal Processing Systems.

[4]  R. P. Brent,et al.  A systolic algorithm for integer GCD computation , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[5]  Uwe Meyer-Baese,et al.  Digital Signal Processing with Field Programmable Gate Arrays , 2001 .

[6]  Uwe Meyer-Baese Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology) , 2004 .

[7]  Peter Zipf,et al.  Dynamically reconfigurable FIR filter architectures with fast reconfiguration , 2013, 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

[8]  Abbes Amira,et al.  A high throughput FPGA implementation of a bit-level matrix product , 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

[9]  S.A. White,et al.  Applications of distributed arithmetic to digital signal processing: a tutorial review , 1989, IEEE ASSP Magazine.

[10]  Peter Zipf,et al.  Reconfigurable FIR filter using distributed arithmetic on FPGAs , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[11]  Damien Stehlé,et al.  A Binary Recursive Gcd Algorithm , 2004, ANTS.

[12]  Peter Zipf,et al.  Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[13]  Michael J. Wirthlin Constant Coefficient Multiplication Using Look-Up Tables , 2004, J. VLSI Signal Process..

[14]  Yasuaki Inoue,et al.  High-performance systolic arrays for band matrix multiplication , 2005, 2005 IEEE International Symposium on Circuits and Systems.