Countermeasures for Timing Attacks
暂无分享,去创建一个
Chester Rebeiro | Debdeep Mukhopadhyay | Sarani Bhattacharya | C. Rebeiro | Debdeep Mukhopadhyay | Sarani Bhattacharya
[1] Debdeep Mukhopadhyay. Cryptanalysis of CLEFIA Using Differential Methods with Cache Trace Patterns , 2011, CT-RSA.
[2] Jean-Pierre Seifert,et al. Deconstructing new cache designs for thwarting software cache-based side channel attacks , 2008, CSAW '08.
[3] Cédric Lauradoux,et al. Collision attacks on processors with cache and countermeasures , 2005, WEWoRC.
[4] Dan Page,et al. Partitioned Cache Architecture as a Side-Channel Defence Mechanism , 2005, IACR Cryptology ePrint Archive.
[5] Chester Rebeiro,et al. An Enhanced Differential Cache Attack on CLEFIA for Large Cache Lines , 2011, INDOCRYPT.
[6] Hovav Shacham,et al. Eliminating fine grained timers in Xen , 2011, CCSW '11.
[7] Ruby B. Lee,et al. Alternative application-specific processor architectures for fast arbitrary bit permutations , 2008, Int. J. Embed. Syst..
[8] M. Martonosi,et al. Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches , 2011, TACO.
[9] Tao Zhang,et al. HIDE: an infrastructure for efficiently protecting information leakage on the address bus , 2004, ASPLOS XI.
[10] Chester Rebeiro,et al. Bitslice Implementation of AES , 2006, CANS.
[11] Adi Shamir,et al. A New Class of Invertible Mappings , 2002, CHES.
[12] Johann Großschädl,et al. Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m) , 2004, CHES.
[13] Rafail Ostrovsky,et al. Software protection and simulation on oblivious RAMs , 1996, JACM.
[14] Johann Großschädl,et al. Instruction set extension for fast elliptic curve cryptography over binary finite fields GF(2/sup m/) , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.
[15] Christophe Clavier,et al. Differential Power Analysis in the Presence of Hardware Countermeasures , 2000, CHES.
[16] Adi Shamir,et al. Cache Attacks and Countermeasures: The Case of AES , 2006, CT-RSA.
[17] Ruby B. Lee,et al. A novel cache architecture with enhanced performance and security , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[18] Jean-Sébastien Coron,et al. Analysis and Improvement of the Random Delay Countermeasure of CHES 2009 , 2010, CHES.
[19] Ruby B. Lee,et al. New cache designs for thwarting software cache-based side channel attacks , 2007, ISCA '07.
[20] Darshana Jayasinghe,et al. Remote Cache Timing Attack on Advanced Encryption Standard and countermeasures , 2010, 2010 Fifth International Conference on Information and Automation for Sustainability.
[21] Eli Biham,et al. A Fast New DES Implementation in Software , 1997, FSE.
[22] Nael B. Abu-Ghazaleh,et al. Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks , 2012, TACO.
[23] Simha Sethumadhavan,et al. TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[24] Sanu Mathew,et al. 53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors , 2010, 2010 Symposium on VLSI Circuits.
[25] Johann Großschädl,et al. Instruction Set Extensions for Pairing-Based Cryptography , 2007, Pairing.
[26] Michael Tunstall,et al. Efficient Use of Random Delays in Embedded Software , 2007, WISTP.
[27] Onur Aciiçmez,et al. Architecting against Software Cache-Based Side-Channel Attacks , 2013, IEEE Transactions on Computers.
[28] Anne Canteaut,et al. Understanding cache attacks , 2006 .
[29] Tao Zhang,et al. Hardware assisted control flow obfuscation for embedded processors , 2004, CASES '04.
[30] Jean-Pierre Seifert,et al. Hardware-software integrated approaches to defend against software cache-based side channel attacks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.
[31] Simha Sethumadhavan,et al. Side-channel vulnerability factor: A metric for measuring information leakage , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[32] Chester Rebeiro,et al. Lightweight cipher implementations on embedded processors , 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
[33] Jean-Sébastien Coron,et al. An Efficient Method for Random Delay Generation in Embedded Software , 2009, CHES.
[34] Ronald L. Rivest,et al. On permutation operations in cipher design , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..