A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling
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[1] Yu Cao,et al. Exploring sub-20nm FinFET design with Predictive Technology Models , 2012, DAC Design Automation Conference 2012.
[2] Alper Demir,et al. SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs , 2011, 2011 Design, Automation & Test in Europe.
[3] Chenming Hu,et al. Direct tunneling leakage current and scalability of alternative gate dielectrics , 2002 .
[4] Yu Cao,et al. Simulation of random telegraph Noise with 2-stage equivalent circuit , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[5] Hamed Abrishami,et al. MUSTARD: A Coupled, Stochastic-Deterministic, Discrete-Continuous Technique for Predicting the Impact of Random Telegraph Noise on SRAMs and DRAMs , 2011 .
[6] C. Mead,et al. White noise in MOS transistors and resistors , 1993, IEEE Circuits and Devices Magazine.
[7] J.S. Suehle,et al. Large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs , 2009, 2009 IEEE International Conference on IC Design and Technology.
[8] D. Sylvester,et al. Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[9] Yiorgos Makris,et al. Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires , 2008, IEEE Transactions on Reliability.
[10] B. Kaczer,et al. Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs , 2007, IEEE Electron Device Letters.
[11] Michael J. Uren,et al. 1/f and random telegraph noise in silicon metal‐oxide‐semiconductor field‐effect transistors , 1985 .
[12] B. L. Bhuva,et al. Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty , 2013, IEEE Transactions on Nuclear Science.
[13] Kuei-Shu Chang-Liao,et al. Study of gate oxide traps in HfO2/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors by use of ac transconductance method , 2013 .
[14] R. Iris Bahar,et al. A Model for Soft Errors in the Subthreshold CMOS Inverter , 2006 .
[15] Naresh R. Shanbhag,et al. Sequential Element Design With Built-In Soft Error Resilience , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Mark Anders,et al. Near-threshold voltage (NTV) design — Opportunities and challenges , 2012, DAC Design Automation Conference 2012.
[17] Joseph L. Mundy,et al. A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic , 2012, GLSVLSI '12.
[18] Diana Marculescu,et al. A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] Gilson I. Wirth,et al. Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants , 2012, Microelectron. Reliab..
[20] Ming Zhang,et al. Combinational Logic Soft Error Correction , 2006, 2006 IEEE International Test Conference.
[21] Alper Demir,et al. Modeling and Simulation of Low-Frequency Noise in Nano Devices: Stochastically Correct and Carefully Crafted Numerical Techniques , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[22] L.W. Massengill,et al. Reducing Soft Error Rate in Logic Circuits Through Approximate Logic Functions , 2006, IEEE Transactions on Nuclear Science.
[23] Cor Claeys,et al. Low frequency noise characterization in n-channel FinFETs , 2012 .
[24] Jiajing Wang,et al. Sub-threshold circuit design with shrinking CMOS devices , 2009, 2009 IEEE International Symposium on Circuits and Systems.
[25] S. Mukhopadhyay,et al. A Simulation Study of Oxygen Vacancy-Induced Variability in ${\rm HfO}_{2}$ /Metal Gated SOI FinFET , 2014, IEEE Transactions on Electron Devices.
[26] L. Garcia-Leyva,et al. Novel redundant logic design for noisy low voltage scenarios , 2013, 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS).
[27] Anantha Chandrakasan,et al. Characterizing and modeling minimum energy operation for subthreshold circuits , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[28] Diana Marculescu,et al. MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).
[29] David V. Anderson,et al. Error Immune Logic for Low-Power Probabilistic Computing , 2010, VLSI Design.
[30] T. Calin,et al. Upset hardened memory design for submicron CMOS technology , 1996 .
[31] Paul K. Hurley,et al. Determination of electron effective mass and electron affinity in HfO2 using MOS and MOSFET structures , 2009 .
[32] Yuan Taur,et al. Fundamentals of Modern VLSI Devices , 1998 .
[33] K. Roy,et al. A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.
[34] Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS , 2012, IEEE Transactions on Electron Devices.
[35] A. Hajimiri,et al. Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.
[36] Joseph L. Mundy,et al. Designing logic circuits for probabilistic computation in the presence of noise , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[37] R. Iris Bahar,et al. A fast simulator for the analysis of sub-threshold thermal noise transients , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[38] L. Kish. End of Moore's law: thermal (noise) death of integration in micro and nano electronics , 2002 .
[39] N. Horiguchi,et al. Low Frequency Noise Analysis for Post-Treatment of Replacement Metal Gate , 2013, IEEE Transactions on Electron Devices.
[40] Ali M. Niknejad,et al. BSIM—SPICE Models Enable FinFET and UTB IC Designs , 2013, IEEE Access.
[41] peixiong zhao,et al. Simulating Nuclear Events in a TCAD Model of a High-Density SEU Hardened SRAM Technology , 2005, 2005 8th European Conference on Radiation and Its Effects on Components and Systems.
[42] Mohan Vamsi Dunga,et al. Nanoscale CMOS modeling , 2008 .
[43] R. Iris Bahar,et al. A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits , 2015, ACM Great Lakes Symposium on VLSI.