Low area memory-free FPGA implementation of the AES algorithm

A new FPGA design for the Advanced Encryption Standard (AES) is presented in this paper. This design is believed to be the smallest memory free FPGA implementation of the AES encryption only requiring 184 slices on a Xilinx Spartan 3 (XC3S50) device, and 80 slices on a Spartan 6 (XC6SLX4) device while achieving throughputs of 36.5Mbps and 58.13Mbps respectively. This FPGA design adopts an 8-bit architecture and exploits the specific fabric in Spartan 3 and Spartan 6 generation FPGAs to optimize the implementation of the shifting operations.

[1]  Sandra Dominikus,et al.  Efficient AES Implementations on ASICs and FPGAs , 2004, AES Conference.

[2]  Dong-Ho Lee,et al.  A Compact Memory-Free Architecture for the AES Algorithm Using Resource Sharing Methods , 2010, J. Circuits Syst. Comput..

[3]  Kris Gaj,et al.  Very Compact FPGA Implementation of the AES Algorithm , 2003, CHES.

[4]  Tim Good,et al.  AES on FPGA from the Fastest to the Smallest , 2005, CHES.

[5]  Keshab K. Parhi,et al.  High-speed VLSI architectures for the AES algorithm , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Panu Hämäläinen,et al.  Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[7]  Jean-Didier Legat,et al.  Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[8]  M. Hannikainen,et al.  Efficient hardware implementation of security processing for IEEE 802.15.4 wireless networks , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..