Routability-driven analytical placement for mixed-size circuit designs

Due to the significant mismatch between existing wirelength models and the congestion objective in placement, considering routability during placement is particularly significant for modern circuit designs. In this paper, a novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs is proposed. Unlike most existing works which usually optimize routability by reallocating whitespace or net-based congestion removal, the proposed algorithm optimizes routability from three major aspects: (1) Pin density: Most existing works optimize routability based on net distribution, while our work considers both the density of pins and their routing directions; (2) Routing overflow optimization: Unlike most previous works that use whitespace allocation or net-based congestion removal to improve routability, our work optimizes routing overflow by a novel sigmoid function during global placement; (3) Macro porosity consideration: A virtual macro expansion technique is applied to consider the constrained routing resource incurred by big macros. Routability-driven legalization and detailed placement are also proposed to further optimize routing congestion. Experimental results show the effectiveness and efficiency of our proposed algorithm. Compared with the participating teams for the 2011 ACM ISPD Routability-Driven Placement Contest, our algorithm achieves the best average overflow and routed wirelength.

[1]  Chris C. N. Chu,et al.  FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Yanheng Zhang,et al.  CROP: Fast and effective congestion refinement of placement , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[3]  Majid Sarrafzadeh,et al.  Routability driven white space allocation for fixed-die standard-cell placement , 2002, ISPD '02.

[4]  Chris C. N. Chu,et al.  FastRoute 2.0: A High-quality and Efficient Global Router , 2007, 2007 Asia and South Pacific Design Automation Conference.

[5]  Jarrod A. Roy,et al.  The ISPD-2011 routability-driven placement contest and benchmark suite , 2011, ISPD '11.

[6]  Jarrod A. Roy,et al.  Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Joseph R. Shinnerl,et al.  Multilevel optimization for large-scale circuit placement , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[8]  Jason Cong,et al.  Routability-driven placement and white space allocation , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[9]  Yao-Wen Chang,et al.  Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[10]  Chris C. N. Chu,et al.  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Peter Spindler,et al.  Fast and accurate routing demand estimation for efficient routability-driven placement , 2007 .

[12]  Chris C. N. Chu,et al.  IPR: An Integrated Placement and Routing Algorithm , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[13]  Andrew B. Kahng,et al.  Implementation and extensibility of an analytic placer , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Jarrod A. Roy,et al.  CRISP: Congestion reduction by iterated spreading during placement , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[15]  Jens Vygen,et al.  BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Yao-Wen Chang,et al.  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Yih-Lang Li,et al.  GRPlacer: Improving routability and wire-length of global routing with circuit replacement , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[18]  Chris C. N. Chu,et al.  FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Peter Spindler,et al.  Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[20]  Jason Cong,et al.  Multilevel generalized force-directed method for circuit placement , 2005, ISPD '05.

[21]  Cheng-Kok Koh,et al.  Guiding global placement with wire density , 2008, ICCAD 2008.