论文信息 - An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications

An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications

An all-digital phase locked loop (ADPLL) with cascaded dynamic phase average (DPA) loop for wide multiplication range applications is presented in this paper. The multiplication factor can range from 4 to 65025 (255 /spl times/ 255). The proposed architecture involves a minimum of hardware and improves jitter performance to reduce the noise and jitter associated with input reference. The dynamic phase averaging (DPA) loop control employing digital phase estimators (DPE) enhances frequency detection resolution and loop stability. A (QR) vector counter and an additional state counter serve as phase estimators. The proposed ADPLL includes cascaded DPA loops: the first stage is low frequency loop and the second stage is high frequency loop. A prototype chip has been implemented with 0.18/spl mu/m 1P6M CMOS process that can operate from 2MHz to 500MHz. The input frequency ranges from 5kHz to 50MHz. Thus it not only reduces the cost and design complexity of ADPLL, but also offers particular advantages for wide multiplication range applications.

Ching-Che Chung | Chen-Yi Lee | Pao-Lung Chen

[1] Hee-Tae Ahn,et al. A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications , 2000, IEEE Journal of Solid-State Circuits.

[2] M. Nakagawa,et al. A new PLL frequency synthesizer with high switching speed , 1992 .

[3] Alain Greiner,et al. A Portable Clock Multiplier Generator using Digital CMOS Standard Cells , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[4] J. Lundberg,et al. An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .

[5] Takamoto Watanabe,et al. An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time , 2003 .

[6] Ching-Che Chung,et al. An all-digital phase-locked loop for high-speed clock generation , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[7] Chen-Yi Lee,et al. Design and analysis of a portable high-speed clock generator , 2001 .

[8] O. Moreira-Tamayo,et al. All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[9] Jaeha Kim,et al. Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL , 2003 .

[10] Ching-Che Chung,et al. A novel digitally-controlled varactor for portable delay cell design , 2004 .