The Counting Algorithm for simulation of million-gate designs

A key part in the development and verification of d igital systems is simulation. But hardware simulators are expensive, and software simulation is not fast enough for designs with a la rge number of gates. As today’s digital designs constantly grow in size (nu mber of gates), and that trend shows no signs to end, faster simulators hand ling millions of gates are needed. We investigate how to create a software gate-level simulator able to simulate a high number of gates fast. This involves a trade-off between memory requirement and speed. A compact netlist rep resentation can utilize cache memories more efficient but requires more work to interpret, while high memory requirements can limit the perfor mance to the speed of main memory. We have selected the Counting Algorithm to implemen t the experimental simulator MICA. The main reasons for this choice is the compact way in which gates can be stored, but still be evaluated i n a simple and standard way. The report describes the issues and solutions encou ntered and evaluate the resulting simulator. MICA simulates a SPARC archite cture processor called Leon. Larger netlists are achieved by simula ting several instances of this processor. Simulation of 128 instances is done at a speed of 9 million gates per second using only 3.5MB memory. In MICA t his design correspond to 2.5 million gates.

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